Generally, in an electronic timepiece, the oscillating signal generated by an oscillating circuit is divided by the dividing circuit to obtain the standard time signal which is counted by the counter, whereby the time is displayed by a digital display or by hands employing a stepping motor. Further, the dividing output and a delayed output obtained from delay circuits employed for delaying the dividing output of the dividing circuit are applied to a gate-circuit. A signal of which the period is equal to the period of the dividing output and the pulse width of which is equal to the delay time of said delay circuit is obtained by said gate-circuit, whereby a level-shifter for obtaining the high voltage for operating the high voltage circuit is controlled by the output signal of the gate-circuit.
In an electronic timepiece of the conventional type, the oscillating signal of the oscillating circuit is employed as the control signal of the delay circuit. Accordingly, if the oscillating condition of the oscillating circuit is changed, malfunctioning of the dividing circuit is caused by the change of wave-shape of the oscillating signal from the normal wave to an irregular wave, whereby the pulse width of the output voltage of the level-shifter becomes narrower, so that the output voltage integrated by the suspended capacity does not attain the desired voltage amplitude. In this condition, the switching operation of an inverter disposed in the input side of high voltage circuit is not operated, whereby the high voltage circuit is not operated in spite of the oscillating operation of the oscillating circuit. Thus, a malfunctioning is caused by the change of output of the oscillating circuit.